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ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 1 g5410 global mixed-mode technology inc. low noise quasi-pwm/pfm asynchronous step down converter features ? +2.8v to +6v input range ? adjustable output from 0.5v to v cc ?1v ? 3a guaranteed output current ? 95% efficiency ? very low quiescent current: 30ua(typ.) ? 100% duty cycle for low dropout mode ? 600khz +-30% quasi pwm operation. ? small, 6-pin sot23 package applications ? desktop and notebook computers ? lan servers ? industrial controls ? pda ? digital still camera ? central office telecom equipment general description the g5410 is a low-noise, quasi pwm/pfm, dc-dc step-down converter. it powers low voltage logic and core in small portable systems such as cellular phones, communicating pdas, and handy-terminals. the device features an internal mosfet driver to be high efficiency buck dc/dc converter. excellent noise characteristics and near fixed frequency operation provide easy post-filtering. the g5410 is ideally suited for li-ion battery applications. it is also useful for +3v or +5v fixed input applications. the device automatic operates in two modes for higher efficiency. pwm mode operates at a fixed frequency regardless of the load. pfm mode extends battery life by switching to a pulse-skipping mode during light loads, it reducing quiescent supply current to under 30a. the g5410 can deliver over 3a. the output voltage can be adjusted from 0.5v to v cc -1v by external ref- erence with the input range of +2.8v to +6v. other features of the g5410 include high efficiency, low dropout mode (100% duty) at input low voltage stage. it is available in a space-saving 6-pin sot23-6 pack- age ordering information part* temp. range pin-package g5410 -40c to +85c sot23-6 pin configuration typical operating circuit gnd vcc gnd vdd sot 23-6 6 4 1 vref 2 3 fb vcc g5410 5 drv vdd drv fb vref c1 0.1f c2 0.1f vcc vref 1 2 3 4 5 6 c4 100f g5410 r3 1m c3 0.1f r2 10k c5 470pf c6 220f vout vdd q1 si3347 l1 5h d1 gnd vcc gnd vdd sot 23-6 6 4 1 vref 2 3 fb vcc g5410 5 drv gnd vdd sot 23-6 6 4 1 vref 2 3 fb vcc g5410 5 drv vdd drv fb vref c1 0.1f c2 0.1f vcc vref 1 2 3 4 5 6 c4 100f g5410 r3 1m c3 0.1f r2 10k c5 470pf c6 220f vout vdd q1 si3347 l1 5h d1
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 2 g5410 global mixed-mode technology inc. absolute maximum ratings v cc to gnd?????..???????.?-0.3v to +7v output short-circuit duration?????.??.?.infinite v dd to gnd.???????????..??-0.3v to +7v v fb to gnd???????..??????.-0.3v to +7v v ref to gnd?.??????..?????..-0.3v to +7v v drv to gnd?????????????.-0.3v to +7v recommend operating range supply voltage (v cc ) ???????....+2.8v to +6.0v driver voltage (v dd ). ?????..??....+2.5v to +v cc continuous power dissipation (t a = +25c) sot23-6??????????????...?..520 mw sot23-6 thermal resistance ja ???..240c/watt junction temperature????????.?.??+150c storage temperature range????..-65c to +160c lead temperature (soldering, 10sec)..?.???+300c electrical characteristics (v cc = 5v; v dd = 5v, v ref =1.8v, t a =25c, unless otherwise noted.) (note1) parameter symbol condition min typ max units v cc input voltage range v cc 2.8 6.0 v v dd driver voltage range v dd 2.5 v cc v quiescent supply current (i cc ) i cc 30 a quiescent supply current (i dd ) i dd 0.2 a i ref v ref =1.8v 0.3 input pin bias current i fb v fb =1.8v 0.3 na input offset voltage v ios v ref =1.8v -10 10 mv v ref operating range v ref -0.3 v cc -1.6 v driver pin high level v oh i oh =10ma v dd -0.1 v driver pin low level v ol i ol =10ma 0.01 v r onh source i source =10ma 7.9 driver resistance r onl sink i sink =10ma 6.1 ? t pgdh v ref =1.8v v fb =v ref +50mv c drv =2200pf 1.2 propagation delay t pgdl v fb =1.8v v ref =v rb +50mv c drv =2200pf 0.6 s note 1: limits is 100% production tested at t a = +25c. low duty pulse techniques are used during test to main- tain junction temperature as close to ambient as possible.
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 3 g5410 global mixed-mode technology inc. overview the g5410 is buck (step-down) dc-dc controller that uses a q-pwm control scheme. the control scheme is designed to quick response to output loading change at the fb pin, the gate drive (drv pin) turns the ex- ternal pfet on or off. when the inductor current is too high, the current limit protection circuit engages and turns the pfet off for approximately 9s. the q-pwm control does not provide an internal oscillator. switch- ing frequency depends on the external components and operating conditions. operating frequency re- duces at light loads resulting in excellent efficiency compared to other architectures. two external resis- tors can easily program the output voltage. the output can be set in a wide range from 0.5v to v in . quasi-pwm/pfm control circuit the g5410 operates in discontinuous conduction mode at light load current or continuous conduction mode at heavy load current. in discontinuous conduc- tion mode, current through the inductor starts at zero and ramps up to the peak, then ramps down to zero. next cycle starts when the fb voltage reaches the internal voltage. until then, the inductor current re- mains zero. operating frequency is lower and switch- ing losses reduce. in continuous conduction mode, current always flows through the inductor and never ramps down to zero. the output voltage (v out ) can be programmed by 2 external resistors. it can be calcu- lated as following. v out = vref x (r1 +r2)/r2 functional description for example, with v out set to 3.3v, v out_pp is 26.6mv v ripple = 0.01 x (33k + 20k) / 20k = 0.0266v operating frequency is determined by knowing the input voltage, output voltage, inductor, vhyst, esr (equivalent series resistance) of output capacitor, and the delay. it can be approximately calculated us- ing the formula: v out (v in -v out ) x esr f = v in x v hyst x x l)+(v in x delay x esr) : (r1+r2) / r2 delay: it includes the g5410 propagation delay time and the pfet delay time. the operating frequency and output ripple voltage can also be significantly influenced by the speed up ca- pacitor (cff). cff is connected in parallel with the high side feedback resistor, r1. the location of this ca- pacitor is similar to where a feed forward capacitor would be located in a pwm control scheme. however it?s effect on hysteretic operation is much different. the output ripple causes a current to be sourced or sunk through this capacitor. this current is essentially a square wave. since the input to the feedback pin, fb, is a high impedance node, the current flows through r2. the end result is a reduction in output ripple and an increase in operating frequency. when adding cff, calculate the formula above with ? = 1. the value of cff depend on the desired operating frequency and the value of r2. a good starting point is 470pf ceramic at 100khz decreasing linearly with increased operating frequency. also note that as the output voltage is pro- grammed below 2.5v, the effect of cff will decrease significantly. design information hysteretic control is a simple control scheme. how- ever the operating frequency and other performance characteristics highly depend on external conditions and components. if either the inductance, output capacitance, esr, v in , or cff is changed, there will be a change in the operating frequency and output ripple. the best approach is to determine what operating frequency is desirable in the application and then be- gin with the selection of the inductor and c out esr.
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 4 g5410 global mixed-mode technology inc. inductor selection (l1) the important parameters for the inductor are the in- ductance and the current rating. the g5410 operates over a wide frequency range and can use a wide range of inductance values. a good rule of thumb is to use the equations used for national?s simple switch- ers ? the equation for inductor ripple as a function of output current is: for i out < 2.0amps di i out x 0.386827 x i out -.366726 for i out > 2.0amps di i out ? 0.3 the inductance can be calculated based upon the de- sired operating frequency where: v in - v ds - v out d l = i x f and v out + v d d = v in - v ds - v d where v d is diode forward voltage. the inductor should be rated to the following: i pk = (i out +di/2 )* 1.1 i rms = 3 i iout 2 2 ? + the inductance value and the resulting ripple is one of the key parameters controlling operating frequency. the second is the esr. output capacitor selection (c out ) the esr of the output capacitor times the inductor ripple current is equal to the output ripple of the regu- lator. however, the v hyst sets the first order value of this ripple. as esr is increased with a given induc- tance, then operating frequency increases as well. if esr is reduced then the operating frequency reduces. the use of ceramic capacitors has become a common de-sire of many power supply designers. however, ceramic capacitors have a very low esr resulting in a 90 phase shift of the output voltage ripple. this re- sults in low operating frequency and increased output ripple. to fix this problem a low value resistor should be added in series with the ceramic output capacitor. although counter intuitive, this combination of a ce- ramic capacitor and external series resistance provide highly accurate control over the output voltage ripple. the other types capacitor, such as sanyo pos cap and os-con, panasonic sp cap, nichicon ?na? se- ries, are also recommended and may be used without additional series resistance. for all practical purposes, any type of output capacitor may be used with proper circuit verification. input capacitor selection (c in ) a bypass capacitor is required between the input source and ground. it must be located near the source pin of the external pfet. the input capacitor prevents large voltage transients at the input and provides the instantaneous current when the pfet turns on. the important parameters for the input capacitor are the voltage rating and the rms current rating. follow the manu-facturer?s recommended voltage derating. for high input voltage application, low esr electrolytic capacitor, the nichicon ?ud? series or the pana- sonic ?fk? series, is available. the rms current in the input capacitor can be calculated. v out x (v in -v out )) 1/2 i rms_cin =i out x v in the input capacitor power dissipation can be calcu- lated as follows. p d ( cin ) = i rms_cin2 x es rcin the input capacitor must be able to handle the rms current and the p d . several input capacitors may be connected in parallel to handle large rms currents. in some cases it may be much cheaper to use multiple electrolytic capacitors than a single low esr, high performance capacitor such as os-con or tantalum. the capacitance value should be selected such that the ripple voltage created by the charge and discharge of the capacitance is less than 10% of the total ripple across the capacitor. catch diode selection the important parameters for the catch diode are the peak current, the peak reverse voltage, and the aver- age power dissipation. the average current through the diode can be calculated as following. i d_ave = i out x (1 - d) the off state voltage across the catch diode is ap- proximately equal to the input voltage. the peak re- verse voltage rating must be greater than input voltage. in nearly all cases a shottky diode is recommended. in low output voltage applications a low forward voltage provides improved efficiency. for high temperature applications, diode leakage current may become sig- nificant and require a higher reverse voltage rating to achieve acceptable performance.
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 5 g5410 global mixed-mode technology inc. p-channel mosfet selection (q1) the important parameters for the pfet are the maxi- mum drain-source voltage (v ds ), the on resistance (r dson ), current rating, and the input capacitance. the voltage across the pfet when it is turned off is equal to the sum of the input voltage and the diode forward voltage. the v ds must be selected to provide some margin beyond the input voltage. drv swings the pfet?s gate from v in to v in - 5v when the input volt- age is greater than 7v. at less than 7v input, the drv voltage swing is smaller. at 4.5v input the drv swings from v in to v in - 3.3v. to insure that the pfet turns on completely, a low threshold pfet should be used when the input voltage is less than 7v. rdson and package size must be used to determine the appropri- ate fet for a given current as well as peak current capability. switching losses also must be considered. the first order losses in the fet are approximately: pdswitch = r dson x i out 2 x d +f x i out x v in x (ton + toff) / 2 where: t on = fet turn on time t off = fet turn off time a value of 10ns to 20ns is typical for ton and t off . the r dson is used in determining the current limit resistor value, r adj . note that the r dson has a positive tem- perature coefficient. at 100c, the rdson may be as much as 150% higher than the 25c value. this in- crease in rdson must be considered it when deter- mining radj in wide temperature range applications. if the current limit is set based upon 25c ratings, then false current limiting can occur at high temperature. keeping the gate capacitance below 2000pf is rec- ommended to keep switching losses and transition times low. as gate capacitance increases, operating frequency should be reduced and as gate capacitance decreases operating frequency can be increased. pcb layout the pc board layout is very important in all switching regulator designs. poor layout can cause switching noise into the feedback signal and general emi prob- lems. for minimal inductance, the wires indicated by heavy lines should be as wide and short as possible. keep the ground pin of the input capacitor as close as possible to the anode of the diode. this path carries a large ac current. the switching node, the node with the diode cathode, inductor, and fet drain, should be kept short. this node is one of the main sources for radiated emi since it is an ac voltage at the switching frequency. it is always good practice to use a ground plane in the design, particularly at high currents. the gate pin of the external pfet should be located close to the drv pin. however, if a very small fet is used, a resistor may be required between drv and the gate of the fet to reduce high frequency ringing. the feedback voltage signal line can be sensitive to noise. make sure to avoid inductive coupling to the inductor or the switch- ing node. block diagram comp + - duty comp vcc vfb ref in vdd drv gnd driver comp + - duty comp vcc vfb ref in vdd drv gnd driver
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 6 g5410 global mixed-mode technology inc. typical performance characteristics (v cc = +5.0v, v dd =+5.0v, c1=c2=0.1f, c4=100f, c6=150f, v ref =1.8v, t a =25c, unless otherwise noted.) 0 5 10 15 20 25 30 35 40 45 50 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 input supply voltage vcc (v) quiescent supply current icc (a) icc @ vdd=3v icc @ vdd=4v icc @ vdd=5v v ref =v cc -2.6v v fb =v ref - 50mv -5 -4 -3 -2 -1 0 1 2 3 4 5 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 vcc supply voltage (v) input bias current (ifb) (na) iref @ vdd=2.6v iref @ vdd=3v iref @ vdd=4v iref @ vdd=5v -5 -4 -3 -2 -1 0 1 2 3 4 5 4.5 4.6 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 5.5 5.6 5.7 5.8 5.9 6.0 vcc input supply voltage (v) input bias current (iref) (na) ifb @ vdd=2.6v ifb @ vdd=3v ifb @ vdd=4v ifb @ vdd=5v -10 -8 -6 -4 -2 0 2 4 6 8 10 4.2 4.4 4.6 4.8 5.0 5.2 5.4 5.6 5.8 6.0 vcc input supply voltage (v) input offset voltage (mv) vios @ vdd=3v vios @ vdd=4v vios @ vdd=5v v ref = 1.8v -10 -8 -6 -4 -2 0 2 4 6 8 10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 driver input voltage (v) input offset voltage (mv) vios @ vcc=4.2v vios @ vcc=4.4v vios @ vcc=5.0v vios @ vcc=5.4v -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vdd (voltage) quiescent supply current idd (a) iddl(ua) vcc=4v iddl(ua) vcc=5v iddl(ua) vcc=5.6v iddl(ua) vcc=6v v ref =v cc -2.6v v fb =v ref - 50mv v ref = 1.8v v fb = 1.8v v ref = 1.8v quiescent supply current (icc) vs. v cc quiescent supply current (idd) vs. v dd input bias current (ifb) vs. v cc input bias current (iref) vs. v cc input offset voltage vs. v cc input offset voltage vs. v dd
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 7 g5410 global mixed-mode technology inc. typical performance characteristics (continued) 0 1 2 3 4 5 6 7 8 9 10 11.522.533.544.555.56 vcc input voltage (v) driver high level v oh (v) voh @ vdd=2.6v voh @ vdd=3.0v voh @ vdd=4.0v voh @ vdd=5.0v 0 1 2 3 4 5 6 7 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 driver input voltage v dd (v) driver output high lever (v) voh @ vcc=3.0v voh @ vcc=4.0v voh @ vcc=4.2v voh @ vcc=5.0v voh @ vcc=5.6v 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 driver input voltage v dd (v) driver ouput low level (v) vol @ vcc=4.0v vol @ vcc=4.2v vol @ vcc=5.0v vol @ vcc=5.6v v ref =v cc -2.6v v fb =v ref + 50mv v ref =v cc -2.6v v fb =v ref - 50mv -0.10 -0.05 0.00 0.05 0.10 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 vcc (voltage) output driver low level vol (v) v ref =v cc -2.6v v fb =v ref - 50mv v ref =v cc -2.6v v fb =v ref - 50mv v ref =v cc -2.6v v fb =v ref + 50mv 5 10 15 20 25 30 35 40 45 50 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 driver input voltage (v) driver on-resistance (high-state) ( ) ronh @ vcc=3.0v ronh @ vcc=4.0v ronh @ vcc=4.5v ronh @ vcc=5.0v v ref =1.8v 4 6 8 10 12 14 16 18 20 22 24 26 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 driver input voltage (v) driver on-resistance (low-state) ( ) ronl @ vcc=3.0v ronl @ vcc=4.0v ronl @ vcc=4.5v ronl @ vcc=5.0v v ref =1.8v driver high level vs. vcc driver low level vs. vcc driver high level vs. v dd driver low level vs. v dd driver on-resistance (high-state) vs. v dd driver on-resistance (low-state) vs. v dd
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 8 g5410 global mixed-mode technology inc. typical performance characteristics (continued) 0 5 10 15 20 25 30 35 40 45 50 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperatu t a (c) quiescent current (icc) (a) icc @ vcc=3v icc @ vcc=4v icc @ vcc=5v v cc =5v,v dd =5v v ref =1.8v v fb =v ref- 50mv -1.00 -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature t a (c) quiescent current (idd) (a) iddh @ vdd=2.5v iddh @ vdd=3.0v iddh @ vdd=3.5v iddh @ vdd=4.0v iddh @ vdd=4.5v iddh @ vdd=5.0v -20 -15 -10 -5 0 5 10 15 20 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) input bias current iref (na) ibiasn@vref=0.2v ibiasn@vref=0.6v ibiasn@vref=1.0v ibiasn@vref=1.4v ibiasn@vref=1.8v ibiasn@vref=2.0v ibiasn@vref=2.4v -15 -13 -11 -9 -7 -5 -3 -1 1 3 5 7 9 11 13 15 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) input bias current ifb (na) ibiasp@vref=0.2v ibiasp@vref=0.6v ibiasp@vref=1.0v ibiasp@vref=1.4v ibiasp@vref=1.8v ibiasp@vref=2.0v ibiasp@vref=2.4v 0 5 10 15 20 25 30 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature ( c) driver on-resistance (high state) ( ) ronh @ vdd=2.5v ronh @ vdd=3.0v ronh @ vdd=3.5v ronh @ vdd=4.0v ronh @ vdd=4.5v ronh @ vdd=5.0v 0 2 4 6 8 10 12 14 16 18 20 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) driver on-resistance (low-state) ( ) ronl @ vdd=2.5v ronl @ vdd=3.0v ronl @ vdd=3.5v ronl @ vdd=4.0v ronl @ vdd=4.5v ronl @ vdd=5.0v v cc =5v,v dd =5v v ref =1.8v v fb =v ref- 50mv v cc =5v, v dd =5v v cc =5v, v dd =5v quiescent current (icc) vs. tempreature quiescent current (idd) vs. tempreature input bias current (iref) vs. temperature input bias current (ifb) vs. temperature driver on-resistance ( hi g h-state ) vs. tem p erature driver on-resistance (low-state) vs. temperature
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 9 g5410 global mixed-mode technology inc. typical performance characteristics (continued) -10 -8 -6 -4 -2 0 2 4 6 8 10 -4 0 -3 5 -3 0 -2 5 -2 0 -1 5 -1 0 -5 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 ambient temperature (c) offset voltage vios(mv) v cc =5v v dd =5v v ref =1.8v input offset voltage vs. temperature propogation delay propogation delay discontinuous mode operation ( v dd 5v, v out 1.8v, 100ma load, 150f tan c out ) continuous mode operation ( v dd 5v, v out 1.8v, 500ma load, 150f tan c out ) continuous mode operation ( v dd 5v, v out 1.8v, 2a load, 150f tan c out )
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 10 g5410 global mixed-mode technology inc. typical performance characteristics (continued) power up wafeworm power off waveform load transient response (0.1a 2a) v cc line transient response (i load =100ma) v cc line transient response (i load =500ma) load transient response (0.1a 0.9a)
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 11 g5410 global mixed-mode technology inc. typical performance characteristics (continued) 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 load current (ma) effieiency (%) vdd=3.0v vdd=3.3v vdd=4.0v vdd=5.0v 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 load current (ma) effieiency (%) vdd=2.5v vdd=3.3v vdd=4.5v vdd=5.0v vdd=5.5v 30 40 50 60 70 80 90 100 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 load current (ma) efficiency (%) vdd=2.5v vdd=3.3v vdd=4.0v vdd=4.5v vdd=5.0v vdd=5.5v 30 40 50 60 70 80 90 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 load current (ma) effieiency (%) vdd=2.5v vdd=3.0v vdd=3.3v vdd=5.0v v dd line transient response (i load =100ma) v dd line transient response (i load =500ma) efficiency vs. load current (v out =2.5v) efficiency vs. load current (v out =1.8v) efficiency vs. load current (v out =1.5v) efficiency vs. load current (v out =1.25v)
ver 0.1 preliminary jul 11, 2002 tel: 886-3-5788833 http://www.gmt.com.tw 12 g5410 global mixed-mode technology inc. package information note: 1. package body sizes exclude mold flash protrusions or gate burrs 2. tolerance 0.1000 mm (4mil) unless otherwise specified 3. coplanarity: 0.1000mm 4. dimension l is measured in gage plane dimensions in millimeters symbols min nom max a 1.00 1.10 1.30 a1 0.00 ----- 0.10 a2 0.70 0.80 0.90 b 0.35 0.40 0.50 c 0.10 0.15 0.25 d 2.70 2.90 3.10 e 1.40 1.60 1.80 e ----- 1.90(typ) ----- h 2.60 2.80 3.00 l 0.37 ------ ----- 1 1o 5o 9o taping specification e e d h 1 l c b a2 a1 a e1 e e d h 1 l c b a2 a1 a e1 feed direction sot 23-6 package orientation feed direction sot 23-6 package orientation

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